The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for interconnects and methods of forming interconnects.
An interconnect structure may be used to electrically connect device structures fabricated by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization formed using a damascene process in which via openings and trenches are etched as interconnect openings in an interlayer dielectric layer and filled with metal to create interconnects in one or more metallization levels.
Copper is a common material used in the metallization of the BEOL portion of the interconnect structure. A barrier/liner layer is required for copper metallization in order to control unwanted diffusion of copper atoms to nearby dielectric materials, such as the interlayer dielectric layer. As the dimensions of interconnects shrink, the resistance of copper interconnects may become unacceptable due to the fraction of the volume of the interconnect opening that is occupied by the barrier/liner layer.
Improved structures for interconnects and methods of forming interconnects are needed.